1. Field of the Invention
This invention relates to a semiconductor integrated circuit fabrication method. More particularly, the present invention relates to a method of forming data storage capacitors with an increased capacitance in a dynamic random access memory (DRAM) of the DRAM cells, so as to maintain a high data retaining capability even if the DRAM chip is reduced in size to achieve higher integration.
2. Description of Related Art
A dynamic random access memory (DRAM) is a volatile semiconductor read/write memory that is widely used as the primary memory in most computers. The information age constantly requires DRAMs with higher integration so as to meet the demands of ever more sophisticated next generation applications. Therefore, it is a continuous research effort in the semiconductor industry to develop DRAMs with higher-packing densities of memory cells in a single DRAM chip.
A single DRAM chip includes a plurality of memory cells, each including at least a MOS transistor and a data storage capacitor (hereinafter referred to as a data storage capacitor) connected in series with the MOS transistor. The data storage capacitor is used to retain electric charges representative of the binary data "0" and "1". These electric charges, however, will be gradually reduced in magnitude due to leakage. Therefore, periodic refreshing of these electric charges is required to enable the data storage capacitor to retain the binary data. It is usually desirable for the data storage capacitor to be formed with a sufficiently high capacitance so that electric charges can be reliably retained for an extended period of time. If the capacitance is too small, data stored in the DRAM cells could be easily lost within a short period of time.
Two approaches to increase the packing density of memory cells in a DRAM chip are presently used: (1) reduce the size of circuit elements of the DRAM chip, such as the length of interconnections and the width of gates of MOS transistors; and, (2) reduce the spacing between individual circuit elements. In future or next generation ULSI (Ultra Large Scale Integration) DRAMs, the data storage capacitors, or more specifically, the charge storage plates (electrodes) used to hold the electric charges will be proportionately reduced in size. It is known from fundamental circuit principles that the capacitance of a capacitor is proportional to the surface area of the charge storage plates. Therefore, a reduction in size of the data storage capacitors in DRAM cells will correspondingly reduce the capacitance of these data storage capacitors, causing these data storage capacitors to retain a reduced amount of electric charges. The binary data stored on the DRAM cells thus could be more easily and quickly lost due to leakage of the electric charges. To retain the data on the data storage capacitors, the DRAM cells need to be more frequently refreshed. However, during the refreshing period, read/write operations cannot be performed, thereby effectively reducing the performance of the DRAM cells. Therefore, in fabricating DRAM cells, it is always desirable to have high capacitance data storage capacitors.
FIG. 1 is a cross-section schematic view of a single DRAM cell having a data storage capacitor formed by a known conventional method. The DRAM cell is fabricated based on a silicon substrate 10, on whose outer major surface a field oxide layer 12 and a gate oxide layer 14 are formed. A first conductive layer, such as a doped polysilicon layer, is formed on the outer surface of the substrate and is then selectively removed to form a gate 16a and a metal contact 16b. Spacers 18a and 18b are then formed respectively on the sidewalls of the gate 16a and of the metal contact 16b. A pair of N.sup.+ source/drain regions 20a and 20b are formed in the silicon substrate 10. An insulating layer 22 is formed over the outer surface of the substrate and then selectively removed to expose the source/drain region 20b.
To form a data storage capacitor for the DRAM cell, a conductive layer 24, a dielectric layer 26, and another conductive layer 28 successively are formed on the outer surface of the substrate, with the layer 24 in contact with the region 20b. Conductive layers 24 and 28 can be, for example, doped polysilicon layers which serve as two opposing electrodes for the data storage capacitor. It is a drawback of the foregoing data storage capacitor that, when the feature size of the DRAM chip is reduced to increase the integration of memory cells on a chip, the surface areas of the conductive layers 24 and 28 will also proportionately be reduced, thus causing a decrease in capacitance of the storage capacitors. This will substantially decrease the charge retaining capability of the data storage capacitor.